CMOS Based ESD Protection Circuit for Low Voltage

Abstract

Electrostatic discharge (ESD) is a common phenomenon, poses a risk to devices and circuits due to their high energy transfer. Catastrophic or latent failures in ICs can result from ESD damage, with latent damage potentially causing malfunctions or premature failure. To safeguard against ESD, protection methods and schemes, such as CMOS -based approaches, are implemented to divert and minimize high currents and voltages, especially as IC technology advances to smaller scales. This project proposed a protection scheme based on 45 nm CMOS technology which was done in Cadence EDA tools. CMOS structures and clamping diode with the implementation of inverter were utilized to reduce peak discharge current and mitigate ESD damage through fast rise times. The Human Body Model (HBM) which is equivalent to 2 kV was used as a testbench for the protection circuit. The first peak current (31.169 mA) of proposed design has results in 97.66 % reduction with the rise time of 55.58 fs, fall time        2.188 ps, and a peak discharge current period of 174.66 fs. The total power dissipation for the DUT is 29.15 mW with circuit layout of 16.81 nm². In summary, the proposed ESD protection circuit can be implemented in the low voltage application.